1. Field of the Invention
The present invention relates to an integrated circuit (IC) having an output buffer.
2. Description of the Prior Art
Integrated circuits that operate at a relatively low power supply voltage (e.g., 3.3 volts) often need to interface with IC's or other components that operate at a higher signal voltage level (e.g., 5 volts). In that case, special attention needs to be paid to the input and output buffers of the low voltage IC. A first concern relates to the fact that the input buffers of the low voltage IC must accept the higher voltage swing (e.g., 0 to 5 volts) and operate properly, while avoiding damage to the transistors of the input buffers. In particular, the gate dielectric (typically an oxide) of a MOS transistor is especially susceptible to damage. This is because the low voltage operation usually requires a very thin gate dielectric (typically less than 100 Angstroms) to maintain high performance, and the 5 volt input signal applied across the dielectric from the gate to the drain, source and/or substrate of the input transistor tends to break down such a thin dielectric. In many cases, an input buffer and an output buffer share a single bondpad, referred to as an input/output (I/O) bondpad. The output buffer may need to supply only the lower voltage (e.g., 3.3 volt) output signal. However, the gate dielectric of the output transistor is also susceptible to breakdown from the higher voltage (e.g., 5 volt) input signal, that may also appear across the gate dielectric of the output transistor.
Various measures have been taken in the prior art to protect the transistors connected to the bondpads from high signal levels. In general, it is known to provide voltage-dropping transistors in series with the transistor being protected. For example, referring to FIG. 1, an input buffer 115 includes an inverter stage comprising complementary CMOS transistor 113 and 114 having their gates connected to the bondpad 100 through the pass transistor 112. The pass transistor 112 provides a voltage drop that reduces the maximum voltage applied to the gate of the protected transistors 113 and 114, while still allowing for transfer of the signal to and from the bondpad. Since the gate of transistor 112 is connected to V.sub.DD in the embodiment shown, the maximum voltage on node 116 is limited to an n-channel transistor threshold (V.sub.tn) below V.sub.DD. Hence, if V.sub.tn =1 volt and V.sub.DD =3.3 volts, then the voltage on inverter input node 116 is limited to 3.3-1=2.3 volts with respect to the negative (ground) power supply voltage V.sub.SS.
Furthermore, the exemplary tri-state output buffer connected to the bondpad 100 includes various protective transistors to protect the p-channel pull-up transistor 102 and n-channel pull-down transistor 104. A first protective p-channel transistor 108 has its gate biased at V.sub.DD -V.sub.tp (where V.sub.tp is the threshold of a p-channel transistor) by transistors 107, 109 and 110. Note that transistor 107 has its backgate connected to V.sub.DD (=3.3 volts), while transistor 108 has its backgate set at V.sub.D5 (=5 volts). This backgate biasing scheme sets the circuit such that the threshold of transistor 108 will always be greater than that of transistor 107, so that when 0 to 3 volt swings are applied to the bondpad, transistor 108 is off. However, when a high voltage (e.g., 5 volt) input signal is present on bondpad 100, transistor 108 conducts, thereby clamping the gate-to-source voltage of transistor 101 at approximately zero volts, protecting the gate to source dielectric and turning off transistor 101. The drain voltage of transistor 101 is charged to V.sub.DD through transistor 102. Therefore, the voltage across the gate to drain dielectric of transistor 101 is limited to the input voltage on the bondpad 100-V.sub.DD. The voltage across the gate to substrate dielectric is limited to the input voltage-V.sub.D5, thereby protecting the dielectric, when the high input voltage is applied to the bondpad.
A second protective transistor 105 is a voltage-dropping pass transistor that protects the pre-driver NAND gate 106 from high signal voltages on the bondpad 100 in the same manner as transistor 112 protects the input stage. The transistor 105 allows sufficient signal drive voltage (0 to V.sub.DD -V.sub.tn) from NAND gate 106 to be applied to the gate of pull-up transistor 101. Transistor 102 is driven by pre-driver NAND gate 106 with voltage swings from 0 to V.sub.DD. Turning off transistor 102 (V.sub.source =V.sub.gate =V.sub.DD) ensures that there is no direct current (DC) path between V.sub.DD and V.sub.SS through transistors 101, 102, 103, 104, and therefore bondpad 100 can be pulled down to a full zero level (V.sub.SS), when transistor 104 is turned on. The protective transistor 103 serves to limit the voltage on the drain of transistor 104 to V.sub.DD -V.sub.tn, thereby protecting it also. The gate to drain voltage of transistor 103 is limited to V.sub.DD minus the input signal voltage.
In order to obtain the desired backgate bias voltage on a given transistor, the transistor may be formed in a doped semiconductor tub region that is connected to the desired power supply voltage conductor (e.g., V.sub.DD or alternatively V.sub.D5), according to techniques known in the art. In most cases, an integrated circuit that implements the inventive output buffer includes power supply terminals for both the buffer power supply voltage (V.sub.DD) and also the power supply voltage that produces the high signal level (V.sub.D5). This is convenient in most cases of mixed-voltage IC's in a given system, since both power supply levels must be supplied in that case anyway. However, in some cases, particularly with portable systems, it may be desirable to generate one of the power supply voltage levels from the other. For example, the low (V.sub.DD) level may be generated by a voltage regulator from the high (V.sub.D5) level. Alternatively, the high level may be generated from the low level by means of a voltage boost circuit, as shown for example in U.S. Pat. No. 5,289,025 coassigned herewith.
A second concern of output buffer design relates to the speed at which they operate, or the propagation delay through the output buffer. In particular, the specification for the peripheral component interface (PCI) bus requires that the propagation delays be minimal, since the allowed delay through the total logic path is 11 nanoseconds. It has been found that an output buffer in accordance with FIG. 1 may not meet this speed requirement, primarily because the pass transistor 105 limits the speed at which the drive signal is applied to the gate of transistor 101. This causes the bondpad 100 to be pulled up to V.sub.DD at a slower speed than if protective transistors were not present.